Auburn Nanosystems Group Dr. Michael C. Hamilton

Cryoelectronics and Systems

We currently have testing capabilities to take samples to a temperature of ~11K and are in the process of acquiring two systems that will allow us to go below a temperature of 4K. We use temperature as a “big knob” in experiments on materials such as CNT, ZnO and GaN to help us understand charge transport through these materials. In addition to looking at how these (and other) materials perform electrically and thermally over a wide range of temperatures, we are also studying how to build better packaging and integration for use in advanced electronic systems at these low temperatures and even lower.

Our ARS cryogenic probe station (made possible by funding provided through the Auburn University Intramural Grants Program, AU-IGP, and the Auburn University College of Engineering) has capabilities including: 4 micromanipulated DC probes, 2 micromanipulated 67GHz GSG probes, 50 pin DC/LF feed through, 4″ sample stage, cryogen-free/closed-cycle He refrigerator, <~11K sample temperature, optical window + microscope + large display, single-button vacuum pump-down. Pump-down in < 1hr, cool-down in < 2hrs.

We are acquiring a Janis LHe Dewar (8CNDT with SVT probe) and performing modifications to our ARS Helitran (flow cryostat) to provide additional temperature-dependent transport and optical microscopy capabilities.

Reworkable Micro & Nano Interconnects

We are exploring the use of different micro and nano structures for use as reworkable contact and interconnect structures. We characterize the power integrity characteristics of large arrays of these structures. Goals for this aspect are to be able to get 100’s of A through arrays of these structures with minimal power loss. We also characterize the signal integrity characteristics of these structures by inserting them between chips with coplanar waveguide leading up to the interconnect. Goals for this aspect are to minimize return / insertion loss for these structures up to 67GHz or 110GHz depending on the desired application. Examples of these reworkable interconnect structures include:

Carbon nanotube bumps (electroplated or ink jet printed SWNT):


Double-Helix Contact Structures (electroplated Cu):

Liquid Metal Interposer (GaIn eutectic liquid metal inside vias of a thin Si wafer into which a Cu pillar array is inserted):


Printed and Solution-Based Electronics

We are exploring multiple methods to realize printed (ink-jet) and solution-based electronics.

As one example, we are developing carbon nanotube inks, using a variety of surfactants (with the help of Dr. Virginia Davis in AU Chemical Engineering):

These, and other inks will be used in our Dimatix materials printer:

A further example is that of solution-based growth of ZnO:


We are performing detailed work on delivering RF and microwave energy efficiently and cleanly to densely integrated systems. We have a very capable set of signal integrity / power integrity (SI / PI) simulation and measurement tools (up to 110GHz & > 28Gbps…see equipment page). With this set of tools, we can simulate the performance of advanced interconnect and integration structures, build them, measure/characterize them and develop models. We use Ansoft (HFSS/Q3D/SIWave), ADS (Momentum/EMPro), Sonnet, etc. to help us to simulate and model these structures.

As an example, we have characterized the power integrity of low-temperature co-fired ceramic (LTCC) power distribution network (PDN) structures. We have found good agreement between the simulated and measured complex impedance up to 3GHz for our PDN structures. (Note there are vias shunting to ground in this structure that appears to be a simple microstrip geometry.)

We also characterize the signal integrity of a host of interconnect and integration structures, ranging from thin-film materials, to LTCC, to advanced bump architectures (chip-to-chip / chip-to-board / chip-to-package). Here we show our bit error rate test (BERT) set-up along with our Cascade Summit RF probe station, as well as a representative >25Gbps eye diagram (note every 4th bit is tested so the bit rate through the structure is 4x that shown) and frequency-domain performance of the differential stripline thin-film structure shown below.